1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming spacers on integrated circuit (IC) products comprised of FinFET devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
In contrast to a planar FET, which, as the name implies, is a generally planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device 10 includes three illustrative fins 14, a gate insulating layer 11, a gate electrode 16, a sidewall spacer 18 and a gate cap 20. A plurality of fin-formation trenches 22 is formed in the substrate 12 to define the fins 14. A recessed layer of insulating material 13 is positioned between the fins 14 and under the gate electrode 16. The overall gate structure is typically comprised of the layer of gate insulating material 11, e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode 16 for the device 10. The fins 14 have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 10 when it is operational, i.e., the gate length (GL) direction of the device 10. Also depicted is the gate width (GW) direction of the device which is transvers to the gate length direction of the device 10. The portions of the fins 14 covered by the gate structure constitute the channel region of the FinFET device 10. The gate structures for such FinFET devices 10 may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques. A FinFET device may have either a tri-gate or dual-gate channel region.
FIGS. 1B-1D are drawings that depict cross-sectional views of the device 10 at various locations so as to explain some problems that may be encountered when forming spacers on FinFET devices using prior art techniques. These drawings include a simplistic plan view of the device 10 (in the upper right corner) that depicts the location where various cross-sectional views depicted in these drawings are taken. More specifically, the view “X-X” is a cross-sectional view taken through an active gate structure (in the gate-width direction) that was formed above the illustrative fins. The view Y-Y is a cross-sectional view taken through a source/drain region of a device 10, i.e., at a location between adjacent gate structures and in a direction that is parallel to the gate width (GW) direction of the device 10. The view “Z-Z” is a cross-sectional view that is taken through the long axis of a fin transverse to the long axis of the gate structures in a direction that corresponds to the current transport or gate length (GL) direction of the devices. Other views are taken where indicated in the attached drawings.
FIG. 1B depicts the product at a point in fabrication wherein four illustrative gate structures 21 were formed above the fins 14. As depicted, the gate insulation layer 11, the gate electrodes 16 and the gate caps 20 have been formed using known techniques.
The next major process operation involves formation of the spacer 18 so as to encapsulate and protect the gate structure. Accordingly, FIG. 1C depicts the product after a layer of spacer material 17 was formed across the entire substrate by performing a conformal deposition process. The layer of spacer material 17 may be comprised of material such as silicon nitride and its thickness may vary. However, it should be noted that as device and overall product dimensions continue to shrink, obtaining a properly formed layer of spacer material is a significant challenge. More specifically, and with reference to FIG. 1B, as the gate pitch 25 on integrated circuit products continues to increase, the space or opening 23 between adjacent gate structures 21 becomes small. Accordingly, all other things being equal, as the aspect ratio of the opening 23 increases, i.e., a ratio of the opening depth 23D to the opening width 23 W, it becomes more difficult to properly fill (i.e., with uniform coverage and thickness) the openings 23 with the layer of spacer material 17.
FIG. 1D depicts the product after one or more anisotropic etching processes were performed to etch the layer of spacer material 17 and thereby define the spacer 18 adjacent the gate structures 21. In an ideal situation, the spacer 18 has an upper surface 18S that is approximately level with the upper surface 20S of the gate cap 20. As depicted, in forming the spacer 18 adjacent the gate structures 21, portions of the layer of spacer material 17 are also removed in the source/drain regions of the devices. That is, at least a portion 26 of the fins 14 in the source/drain regions are exposed after the spacer etch process. After the formation of the spacer 18 adjacent the gate structures 21, the normal process flow would include growing epi semiconductor material 27 (shown in dashed lines in FIG. 1D) on the exposed portions of the fins 14 in the source/drain regions.
With continuing reference to FIG. 1D, one problem that occurs is that, in some cases, the size of the exposed portion of the fins 14 in the source/drain regions is very small, e.g., the dimension 26 may be on the order of about 10-30 nm. Stated another way, too much of the layer of spacer material 17 remains positioned adjacent the fins 14 in the source/drain region at the completion of the formation of the spacer 18 adjacent the gate structures 21. Due to the limited size of the exposed portion of the fins 14, the size of the epi semiconductor material 27 may be less than would otherwise be desired, thereby perhaps resulting in less than preferred device performance. One possible solution would be to simply increase the duration of the spacer etch process so as to insure that the spacer material is removed from the fins 14 in the source/drain regions. But, one risk to this approach would be consuming too much of the spacer 18 adjacent the gate structures 21, i.e., there would be too much “pull-down” (a decrease in overall height) of the spacer 18. In a worst case scenario, if there is too much pull-down of the spacer 18, portions of the gate electrode 16 may be exposed and subject to later attack in later processing operations. One way to counter-act this potential for excessive pull-down of the spacer 18 is to make the gate cap 20 thicker, e.g., with an upper surface 20X, which, in turn, would effectively increase the overall idealized height of this taller spacer 18A (shown in dashed lines), with an upper spacer 18X. By making the extra tall spacer 18A, the duration of the spacer etch process could be increased in an effort to remove significantly more or all of the layer of spacer material 17 from adjacent the fins 14 in the source/drain regions so that more of the fin is exposed for formation of the epi material 27. For example, the spacer etch process could be performed until such time as the extra tall spacer 18A has an upper surface 18Y that is positioned slightly above the upper surface 16S of the gate electrode 16. Unfortunately, this proposed “solution” would only further increase the aspect ratio of the space 23 between adjacent gate structures 21, thereby making the filling of the spaces 23 with the layer of spacer material 17 even more challenging.
The present disclosure is directed to methods of forming spacers on integrated circuit (IC) products comprised of FinFET devices that may solve or reduce one or more of the problems identified above.